Engineering Halloween
He only pokes fun at Marketing a little bit this time. I must confess, I once dressed as an integrated circuit for Halloween. It was in college and I was a DIP. Maybe that's why it didn't impress the girls? Have a great weekend.

Are You Listening?
When I'm out and about doing chores or exercising, chances are I'll be listening to my iPod. But more often than not, I'm listening to podcasts rather than music. Listening to podcasts is an efficient way of "reading on the go". You can catch up on the latest news stories, political opinions, or investment ideas. Those are my interests; you can find a podcast on practically any topic. Have you listened to podcasts? Which are your favorites? In our field of semiconductor engineering, there's

Synopsys Users' Group CFP
As you may have heard me say (write) before, the Synopsys Users' Group (SNUG) conference is the most useful conference I attend each year. If you're involved in chip design and haven't attended, you really need to check it out. There are conferences around the world, but the biggest one is in Silicon Valley every March. Why am I bringing this up now? Because the Synopsys Users Group - San Jose Call for Papers is open! Here's a chance to show your chops and burnish your resume by demonstrating the cool stuff you're doing with Synopsys tools. The authors get a lot of support from the experience Technical Committee [f

Career Thoughts
Taking a break from the technical, career issues merit reflection and discussion. Here are some brief thoughts. How's the Market? What's your perception of the ASIC/EDA jobs market? My take is that it's pretty weak, but a number of companies are "selectively hiring". I had a couple of friends leave their struggling design services firm, and they were able to land jobs at established growing companies within a couple of months. On the other hand, there are plenty of engineers who have been looking for many months. One differentiator is that hiring favors leading-edge experience (e.g., expert P&R and design closure of 65 or 45nm chips), or knowledge (e.g., advanced degree wi

Everybody's Getting Physical
Image courtesy Wikimedia. Back before "nanometer design", there was "deep submicron design", and ASIC synthesis users became very concerned about interconnect effects on timing. The first attempt to deal with this was through "Links to Layout", and especially a whole slew of custom wireload model (CWLM) strategies. If you look at SNUG programs a number of years ago, there were